Mass Production Begins
China's DRAM manufacturer CXMT has initiated mass production utilizing its 5th-generation DRAM process technology.
CXMT states that its new G5 process technology reduces the DRAM active-area half-pitch to 11.95nm through quadruple-patterning lithography. The 11.95nm half-pitch equates to an active-area pitch of 23.9nm, placing this metric within the range of other advanced 10nm-class DRAM technologies, though it does not translate directly into a conventional node designation. Additionally, CXMT reports that its DRAM-optimized high-K metal gate process decreased the height of the core cell array to 6,762nm.
Capacitor Design
The company also altered its process flow and incorporated new materials to support storage capacitors with a depth-to-width aspect ratio of approximately 45:1. While difficult to compare directly against competing technologies, SK hynix has previously indicated that capacitor aspect ratios will need to exceed 100:1 as DRAM critical dimensions drop below 10nm.
A 45:1 aspect ratio means CXMT's storage capacitors are 45 times deeper than they are wide, facilitating a reduction in DRAM cell area and allowing more memory arrays to fit onto a single wafer. However, elevated aspect ratios introduce significant fabrication challenges related to etching, deposition, mechanical stability, and high-yield manufacturing.
First G5 Products
The initial mass-produced devices utilizing the G5 process are 24Gb LPDDR5X chips. These components offer a 50% capacity increase over prior comparable products and are produced in two package formats for mobile device architectures, with deployment underway in flagship smartphones.
Technical Caveats and Yields
Several caveats accompany the milestone. The 11.95nm metric reflects the active-area half-pitch rather than a standard process node designation, making the 12nm classification a simplification.
Furthermore, these physical dimensions do not automatically denote technological parity with advanced DRAM processes from Micron, Samsung, and SK hynix, given that density, capacitor scaling, transistor characteristics, power consumption, and manufacturing yields dictate commercial viability. Although CXMT claims the G5 process yields at least 50% more gross dies per wafer than G4, specific volume numbers and yield data were not disclosed, leaving actual productivity gains and manufacturing costs per bit unverified.
