The Path to FDX Fusion
Eight years after GlobalFoundries abandoned the development of its 7nm FinFET technology, the company is preparing to return to 7nm-class performance, this time by going via a different route. Its FDX Fusion process, built on FD-SOI (fully depleted silicon-on-insulator) technology, promises 7nm-class performance using advanced planar transistors, with no EUV lithography necessary.
GlobalFoundries' vice president of the FD-SOI business unit, Sudipto Bose, shared new details about its FDX Fusion technology, including its 8nm-class logic density, advanced planar transistors, manufacturing costs, and plans to begin commercial production in 2028. The company also explained how it intends to compete with conventional FinFET technologies and why it believes FD-SOI has a future beyond the 22nm-class generation.
Bose has been at GlobalFoundries for over six years, following a long career at Texas Instruments. His focus has transitioned from the automotive segment to the FDX product line.
GlobalFoundries has been investing in FD-SOI for nearly eight years. The investment thesis for FDX Fusion is driven by significant market traction, with high double-digit customer counts currently ramping up on existing FD-SOI platforms.
Applications for FDX Fusion
FDX Fusion is designed to enhance existing application areas, including connectivity (Wi-Fi, Bluetooth, cellular, and satcom), edge AI processors, and automotive radar. The technology also targets data center connectivity, specifically for signal amplification and clock recovery circuits.
The company emphasizes that FDX Fusion is not intended for CPUs, but rather for data and signal paths that feed into compute chips within the data center.
7nm-class FD-SOI node
GlobalFoundries' FDX Fusion promises 8nm-class logic density and 7nm-class power and performance without EUV lithography or FinFET transistors, reducing design and manufacturing costs.
The process utilizes advanced planar FD-SOI transistors, strained silicon substrates, and aggressive optical patterning to reach dimensions comparable to 8nm-class FinFET nodes.
FDX Fusion supports adaptive body biasing and integrates high-density digital logic with RF, analog, and embedded memory. While it uses DUV lithography, the tight gate and metal pitches will likely require extensive multipatterning.
Key improvements include an fT/fmax of 500 GHz to support high-speed data connectivity and a 2.2x increase in digital gate density compared to the 22FDX generation.
The platform offers a gate density of 14 million gates per square millimeter.
By utilizing adaptive body bias and standard cell metallization innovations, GlobalFoundries targets TOPS per watt performance equivalent to or better than 7nm nodes, while avoiding the high costs associated with EUV mask sets.
New tools required
FDX Fusion will require new tool investments at the Dresden facility, particularly for lithography, etching, and metrology. The company is currently working with vendors to define the necessary configurations.
Initial customer production is targeted for 2028, with high-volume manufacturing expected to reach maturity by 2030.
Readiness
GlobalFoundries plans to release the initial FDX Fusion PDK in mid-2027 and is currently in discussions with major EDA vendors to ensure comprehensive design flow support.
ARC, MIPS, and Fusion FDX
The company is leveraging its RISC-V expertise and MIPS processor IP to accelerate the development cycle. MIPS is expected to launch platforms specifically fine-tuned for FDX Fusion.
Costs
GlobalFoundries aims for a running cost significantly better than 7nm or 6nm designs by avoiding EUV masks and utilizing planar transistors. The goal is to provide a cost-competitive alternative for applications requiring multiple tape-outs.
The future of FDX
Future iterations of FDX Fusion are expected to incorporate advancements in eNVM, EDA routing, chip folding, and 2.5D integration, though specific timelines remain dependent on customer feedback and lab maturation.
CEA-Leti involvement
FDX Fusion is described as an internally developed node by GlobalFoundries, though it incorporates substrate engineering work conducted in collaboration with Soitec and CEA-Leti.
Under the FAMES program, the partners are developing strained silicon substrates to improve charge carrier mobility. This technology has been validated in the laboratory and is currently being refined for high-volume manufacturing.
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