Micron Reveals Ambitious DRAM and NAND Roadmap for AI Era

Micron disclosed its DRAM and NAND memory roadmaps, revealing plans to use wafer bonding, new materials for smaller NAND cells, High-NA EUV lithography, and moves toward 3D DRAM. The company also plans to expand its portfolio of custom DRAM and NAND products as AI developers require memory and storage solutions optimized for unique processor architectures.

DRAM is nearing atomic limits, and Micron is focused on introducing 3D DRAM at the optimal time from a cost and performance point of view. For 3D NAND, the company is focused on new materials densifying the cell architecture and continuing XYZ scaling.

DRAM Roadmap

Micron decided to abandon plans to produce DRAM with 4F2 memory cells due to a lack of a viable scaling path. Instead, the roadmap includes wafer bonding, High-NA EUV lithography, new materials, and eventually 3D DRAM. Mass production of the next-generation 1δ memory is planned for the second half of 2027.

Micron's current 1γ DRAM process technology in high-volume manufacturing is the company's first DRAM node to use EUV lithography, following previous reliance on multipatterning DUV.

The next-generation 1δ fabrication process is scheduled for mass production in the second half of 2027, increasing bit density by the mid-20% range compared to 1γ while improving performance and power efficiency via high-k metal gate CMOS.

Micron plans to manufacture 1δ DRAM in the U.S. for next-generation DDR, LPDDR, graphics memory, HBM5, vertical HBM, and vertical Edge Inference Memory products.

The subsequent 1ε process will rely on wafer bonding to produce different structures on separate wafers before bonding them together, increasing flexibility in memory design and manufacturing.

The ζÅ production node will introduce High-NA EUV lithography to memory manufacturing, enabling further reductions in critical dimensions, though it is not expected until at least 2030.

The ηÅ process is in the pathfinding stage, utilizing new materials such as advanced photoresists, deposition precursors, and dielectric materials to manufacture smaller transistors and capacitors.

Micron's roadmap focuses on continuing the development of DRAM based on 6F² cells, differing from the approach taken by some industry competitors.

3D DRAM Development

In parallel with conventional DRAM, Micron is working on two generations of 3D DRAM called 3D1 and 3D2. These architectures utilize the vertical dimension to accommodate more memory cells within a given area once the technology reaches commercial viability.

While Micron outlined its architectures through 2030, a firm production window has only been established for the 1δ process scheduled for high-volume manufacturing in late 2027.

Custom Memory Solutions

Micron plans to use future manufacturing technologies for HBM4E, HBM5, HBM5E, and vertically integrated memory architectures, marking the re-emergence of custom memory in mass-produced products.

Custom HBM4E will enable customers to shrink memory I/O width or integrate logic into the base die to free up space for compute, optimizing performance and power consumption for AI accelerators.

Co-designing base dies allows specific logic elements to be offloaded from GPU circuitry directly onto the memory base die to improve system efficiency.

Micron intends to use advanced foundry process technologies for base dies, selecting cost-effective processes tailored to customer performance and power targets.

Vertical HBM will stack memory directly on top of ASICs and CPUs rather than next to them on an interposer, promising higher bandwidth and lower latencies alongside thermal management challenges addressed via hybrid bonding.

Vertical Edge Inference Memory targets applications requiring high power efficiency, aiming to deliver 2 TB/s of bandwidth while consuming less than 1 picojoule per bit.

Both architectures require close collaboration with customers to optimize memory, logic, packaging, and thermal characteristics for specific enterprise applications.

Micron is collaborating with Meta to optimize LPDDR6 for data center applications to reduce power consumption by approximately 35% compared to LPDDR5, alongside developing DDR6 to target double the bandwidth of DDR5.

Customer cooperation spans from early product definition through joint design, development, validation, and volume production.

AI co-invention opportunities involve co-imagining, co-designing, co-developing, and co-validating products to deliver scalable solutions tailored to modern computing demands.

CMOS Advancements

Micron is developing advanced CMOS technologies for peripheral circuitry, including several generations of DRAM CMOS logic with high-k metal gate transistors and 3D CMOS technologies.

These advances are expected to increase CMOS logic performance by more than 10X between 2020 and 2030 to address bandwidth and power requirements of AI memory products.

NAND Innovations

Micron shared details on upcoming NAND innovations, including 11th Generation 3D NAND with over 400 layers, post-G11 developments, and AI-oriented NAND memory focused on high bandwidth or high IOPS.

The next-generation G11 3D NAND technology increases active memory layers from 276 to over 400, introduces wafer-on-wafer bonding, and implements an industry-leading cell pitch.

G11 aims to double the bit density of G9 3D NAND, reducing manufacturing costs per bit once mature yields are reached.

G11 targets a 50% increase in I/O speed up to 5,400 MT/s and a 25% reduction in data transfer energy consumption per bit for high-capacity SSDs.

Wafer-on-wafer bonding allows Micron to manufacture memory arrays and peripheral I/O circuits on separate wafers and bond them together.

Mass production of G11 3D NAND is scheduled to begin in the second half of 2027.

Future NAND Materials and XYZ Scaling

Beyond the 11th Generation, Micron is investigating high-mobility materials to improve electrical characteristics and ultra-dense cell architectures to increase storage density.

Energy-efficient circuitry and data paths help offset power consumption associated with higher NAND capacities and faster interfaces.

Roadmap execution focuses on new materials, densifying cell architecture, and XYZ scaling by adding layers and shrinking cell dimensions.

Specific material compositions and quantitative density targets for generations beyond G11 remain undisclosed.

AI-Oriented NAND Architectures

Micron is developing specialized NAND architectures tailored for AI applications to handle demanding vector searches, graph analytics, and context management.

High-IOPS AI NAND focuses on random I/O performance using SLC-based designs to deliver between 25 million and 100 million IOPS.

High-Bandwidth AI NAND prioritizes bandwidth by utilizing vertically stacked NAND devices connected through TSVs with a logic base die placed close to compute resources.

Positioning TSV-stacked NAND closer to compute resources avoids consuming the perimeter shoreline of GPUs.

These AI-focused NAND architectures complement a conventional SSD roadmap featuring planned capacities of up to 512 TB.